-------------------------------------------------------------------------------
-- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- 
-- 
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 7.1i
--  \   \         Application : 
--  /   /         Filename : aurora_interface_0_GTP_WRAPPER.vhd
-- /___/   /\     Timestamp : 02/16/2005 10:19:02
-- \   \  /  \ 
--  \___\/\___\ 
--------------------------------------------------------------------------------
--Command: 
--Design Name: aurora_interface_0_GTP_WRAPPER
--
-- Module aurora_interface_0_GTP_WRAPPER
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity aurora_interface_0_GTP_WRAPPER is
generic
(
    --Simulation attributes
    SIM_GTPRESET_SPEEDUP :integer :=   0      --Set to 1 to speed up sim reset
);
port
(
---------------------- Loopback and Powerdown Ports ----------------------
LOOPBACK_IN_0                               : in    std_logic_vector (2 downto 0);
LOOPBACK_IN_1                               : in    std_logic_vector (2 downto 0);
--------------------- Receive Ports - 8b10b Decoder ----------------------

RXCHARISCOMMA_OUT_0 : out   std_logic_vector (3 downto 0); 
RXCHARISCOMMA_OUT_1 : out   std_logic_vector (3 downto 0); 
RXCHARISK_OUT_0     : out   std_logic_vector (3 downto 0);
RXCHARISK_OUT_1     : out   std_logic_vector (3 downto 0);
RXDISPERR_OUT_0     : out   std_logic_vector (3 downto 0);
RXDISPERR_OUT_1     : out   std_logic_vector (3 downto 0);
RXNOTINTABLE_OUT_0  : out   std_logic_vector (3 downto 0);
RXNOTINTABLE_OUT_1  : out   std_logic_vector (3 downto 0);
----------------- Receive Ports - Channel Bonding Ports -----------------

ENCHANSYNC_IN     : in    std_logic;

CHBONDDONE_OUT    : out   std_logic;

----------------- Receive Ports - Clock Correction Ports -----------------

RXBUFERR_OUT_0      : out   std_logic;
RXBUFERR_OUT_1      : out   std_logic;

------------- Receive Ports - Comma Detection and Alignment --------------

RXREALIGN_OUT_0     : out   std_logic;
RXREALIGN_OUT_1     : out   std_logic;

ENMCOMMAALIGN_IN_0  : in    std_logic;
ENMCOMMAALIGN_IN_1  : in    std_logic;

ENPCOMMAALIGN_IN_0  : in    std_logic;
ENPCOMMAALIGN_IN_1  : in    std_logic;

----------------- Receive Ports - RX Data Path interface -----------------
RXDATA_OUT_0        : out   std_logic_vector (31 downto 0);
RXDATA_OUT_1        : out   std_logic_vector (31 downto 0);

RXRECCLK1_OUT     : out   std_logic;

RXRECCLK2_OUT     : out   std_logic;

RXRESET_IN_0        : in    std_logic;
RXRESET_IN_1        : in    std_logic;
RXUSRCLK_IN_0                               : in    std_logic;
RXUSRCLK_IN_1                               : in    std_logic;
RXUSRCLK2_IN_0                              : in    std_logic;
RXUSRCLK2_IN_1                              : in    std_logic;
----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------

RX1N_IN_0           : in    std_logic;
RX1N_IN_1           : in    std_logic;
RX1P_IN_0           : in    std_logic;
RX1P_IN_1           : in    std_logic;

--------------- Receive Ports - RX Polarity Control Ports ----------------
RXPOLARITY_IN_0     : in    std_logic;
RXPOLARITY_IN_1     : in    std_logic;

------------------- Shared Ports - Tile and PLL Ports --------------------

REFCLK                                    : in    std_logic;

GTPRESET_IN                               : in    std_logic;
PLLLKDET_OUT_0      : out   std_logic;
PLLLKDET_OUT_1      : out   std_logic;
-------------- Transmit Ports - 8b10b Encoder Control Ports --------------

TXCHARISK_IN_0      : in    std_logic_vector (3 downto 0);
TXCHARISK_IN_1      : in    std_logic_vector (3 downto 0);

---------------- Transmit Ports - TX Data Path interface -----------------

TXDATA_IN_0         : in    std_logic_vector (31 downto 0);
TXDATA_IN_1         : in    std_logic_vector (31 downto 0);

GTPCLKOUT_OUT_0     : out   std_logic_vector(1 downto 0);
GTPCLKOUT_OUT_1     : out   std_logic_vector(1 downto 0);
TXRESET_IN_0        : in    std_logic;
TXRESET_IN_1        : in    std_logic;
 
TXUSRCLK_IN_0                               : in    std_logic;       
TXUSRCLK_IN_1                               : in    std_logic;       
TXUSRCLK2_IN_0                              : in    std_logic;
TXUSRCLK2_IN_1                              : in    std_logic;
TXBUFERR_OUT_0      : out   std_logic;
TXBUFERR_OUT_1      : out   std_logic;

------------- Transmit Ports - TX Driver and OOB signalling --------------

TX1N_OUT_0          : out   std_logic;
TX1N_OUT_1          : out   std_logic;
TX1P_OUT_0          : out   std_logic;
TX1P_OUT_1          : out   std_logic;


------------------- Receive Ports - Channel Bonding Ports -----------------
CHBONDDONE_OUT_unused    : out   std_logic;


POWERDOWN_IN_0                                       : in    std_logic;                  
POWERDOWN_IN_1                                       : in    std_logic                  

);
end aurora_interface_0_GTP_WRAPPER;

architecture BEHAVIORAL of aurora_interface_0_GTP_WRAPPER is
  attribute core_generation_info               : string;
  attribute core_generation_info of BEHAVIORAL : architecture is "aurora_interface_0,aurora_8b10b_v6_2,{user_interface=AXI_4_Streaming, backchannel_mode=Sidebands, c_aurora_lanes=1, c_column_used=None, c_gt_clock_1=GTPD2, c_gt_clock_2=None, c_gt_loc_1=X, c_gt_loc_10=X, c_gt_loc_11=X, c_gt_loc_12=X, c_gt_loc_13=X, c_gt_loc_14=X, c_gt_loc_15=X, c_gt_loc_16=X, c_gt_loc_17=X, c_gt_loc_18=X, c_gt_loc_19=X, c_gt_loc_2=X, c_gt_loc_20=X, c_gt_loc_21=X, c_gt_loc_22=X, c_gt_loc_23=X, c_gt_loc_24=X, c_gt_loc_25=X, c_gt_loc_26=X, c_gt_loc_27=X, c_gt_loc_28=X, c_gt_loc_29=X, c_gt_loc_3=X, c_gt_loc_30=X, c_gt_loc_31=X, c_gt_loc_32=X, c_gt_loc_33=X, c_gt_loc_34=X, c_gt_loc_35=X, c_gt_loc_36=X, c_gt_loc_37=X, c_gt_loc_38=X, c_gt_loc_39=X, c_gt_loc_4=X, c_gt_loc_40=X, c_gt_loc_41=X, c_gt_loc_42=X, c_gt_loc_43=X, c_gt_loc_44=X, c_gt_loc_45=X, c_gt_loc_46=X, c_gt_loc_47=X, c_gt_loc_48=X, c_gt_loc_5=1, c_gt_loc_6=X, c_gt_loc_7=X, c_gt_loc_8=X, c_gt_loc_9=X, c_lane_width=4, c_line_rate=3.125, c_nfc=false, c_nfc_mode=IMM, c_refclk_frequency=156.25, c_simplex=false, c_simplex_mode=TX, c_stream=true, c_ufc=false, flow_mode=None, interface_mode=Streaming, dataflow_config=Duplex}";
--***************************** Compopnent Declaration ****************************
component AURORA_INTERFACE_0_TILE is
generic
(
    -- Simulation attributes
    TILE_SIM_GTPRESET_SPEEDUP    : integer   := 0 -- Set to 1 to speed up sim reset
);
port 
(
    ------------------------ Loopback and Powerdown Ports ----------------------
    LOOPBACK0_IN                            : in   std_logic_vector(2 downto 0);
    LOOPBACK1_IN                            : in   std_logic_vector(2 downto 0);
    RXPOWERDOWN0_IN   	                    : in   std_logic_vector(1 downto 0);
    RXPOWERDOWN1_IN   	                    : in   std_logic_vector(1 downto 0);
    TXPOWERDOWN0_IN   	                    : in   std_logic_vector(1 downto 0);
    TXPOWERDOWN1_IN   	                    : in   std_logic_vector(1 downto 0);
    ----------------------- Receive Ports - 8b10b Decoder ----------------------
    RXCHARISCOMMA0_OUT 		     	    : out std_logic_vector(3 downto 0);
    RXCHARISCOMMA1_OUT 		     	    : out std_logic_vector(3 downto 0);
    RXCHARISK0_OUT 		     	    : out std_logic_vector(3 downto 0);
    RXCHARISK1_OUT 		     	    : out std_logic_vector(3 downto 0);
    RXDISPERR0_OUT 		     	    : out std_logic_vector(3 downto 0);
    RXDISPERR1_OUT 		     	    : out std_logic_vector(3 downto 0);
    RXNOTINTABLE0_OUT 		     	    : out std_logic_vector(3 downto 0);
    RXNOTINTABLE1_OUT 		     	    : out std_logic_vector(3 downto 0);
    ------------------- Receive Ports - Clock Correction Ports--
    RXCLKCORCNT0_OUT			    : out std_logic_vector(2 downto 0);
    RXCLKCORCNT1_OUT			    : out std_logic_vector(2 downto 0);
    --------------- Receive Ports - Comma Detection and Alignment --------------
    RXBYTEREALIGN0_OUT			    : out std_logic;
    RXBYTEREALIGN1_OUT			    : out std_logic;
    RXENMCOMMAALIGN0_IN			    : in std_logic;
    RXENMCOMMAALIGN1_IN			    : in std_logic;
    RXENPCOMMAALIGN0_IN			    : in std_logic;
    RXENPCOMMAALIGN1_IN			    : in std_logic;
    ------------------- Receive Ports - RX Data Path interface -----------------
    RXDATA0_OUT                             : out  std_logic_vector(31 downto 0);
    RXDATA1_OUT                             : out  std_logic_vector(31 downto 0);
    RXRESET0_IN                             : in   std_logic;
    RXRESET1_IN                             : in   std_logic;
    RXUSRCLK0_IN                            : in   std_logic;
    RXUSRCLK1_IN                            : in   std_logic;
    RXUSRCLK20_IN                           : in   std_logic;
    RXUSRCLK21_IN                           : in   std_logic;
    ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
    RXN0_IN                                 : in   std_logic;
    RXN1_IN                                 : in   std_logic;
    RXP0_IN                                 : in   std_logic;
    RXP1_IN                                 : in   std_logic;
    -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
    RXBUFSTATUS0_OUT                        : out  std_logic_vector(2 downto 0);
    RXBUFSTATUS1_OUT                        : out  std_logic_vector(2 downto 0);
    TXBUFSTATUS0_OUT                        : out  std_logic_vector(1 downto 0);
    TXBUFSTATUS1_OUT                        : out  std_logic_vector(1 downto 0);
    ----------------- Receive Ports - RX Polarity Control Ports ----------------
    RXPOLARITY0_IN                          : in   std_logic;
    RXPOLARITY1_IN                          : in   std_logic;
    --------------------- Shared Ports - Tile and PLL Ports --------------------
    CLK00_IN                                : in   std_logic;
    CLK01_IN                                : in   std_logic;
    GTPRESET0_IN                            : in   std_logic;
    GTPRESET1_IN                            : in   std_logic;
    PLLLKDET0_OUT                           : out  std_logic;
    PLLLKDET1_OUT                           : out  std_logic;
    RESETDONE0_OUT                          : out  std_logic;
    RESETDONE1_OUT                          : out  std_logic;
    ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
    TXCHARISK0_IN			    : in std_logic_vector(3 downto 0);
    TXCHARISK1_IN			    : in std_logic_vector(3 downto 0);
    -------------- Transmit Ports - 64b66b and 64b67b Gearbox Ports ------------
    TXDATA0_IN                              : in   std_logic_vector(31 downto 0);
    TXDATA1_IN                              : in   std_logic_vector(31 downto 0);
    GTPCLKOUT0_OUT                          : out  std_logic_vector(1 downto 0);
    GTPCLKOUT1_OUT                          : out  std_logic_vector(1 downto 0);
    TXRESET0_IN                             : in   std_logic;
    TXRESET1_IN                             : in   std_logic;
    TXUSRCLK0_IN                            : in   std_logic;
    TXUSRCLK1_IN                            : in   std_logic;
    TXUSRCLK20_IN                           : in   std_logic;
    TXUSRCLK21_IN                           : in   std_logic;
    --------------- Transmit Ports - TX Driver and OOB signalling --------------
    TXN0_OUT                                : out  std_logic;
    TXN1_OUT                                : out  std_logic;
    TXP0_OUT                                : out  std_logic;
    TXP1_OUT                                : out  std_logic
);
end component;

   signal tied_to_ground_i                                : std_logic;
   signal tied_to_ground_vec_i                            : std_logic_vector (63 downto 0);
   signal tied_to_vcc_i                                   : std_logic;
   signal open_rxbufstatus_0        : std_logic_vector (1 downto 0);
   signal open_rxbufstatus_1        : std_logic_vector (1 downto 0);
   signal open_txbufstatus_0        : std_logic;
   signal open_txbufstatus_1        : std_logic;
   signal open_rxbufstatus_lane1        : std_logic_vector (1 downto 0);
   signal open_txbufstatus_lane1        : std_logic;
   --signal to output lock signal
   signal plllkdet_lane0_i                                      : std_logic;
   signal plllkdet_lane1_i                                      : std_logic;
  
   signal  resetdone0_i            : std_logic;
   signal  resetdone1_i            : std_logic;
 
begin

   tied_to_ground_i <= '0';
   tied_to_ground_vec_i(63 downto 0) <= x"0000000000000000";
   tied_to_vcc_i <= '1';

--Assign lock signals
  PLLLKDET_OUT_0  <=   plllkdet_lane0_i;
  PLLLKDET_OUT_1  <=   plllkdet_lane1_i;






--*************************************************************************************************    
-------------------------------------EVEN GTP-----------------------------------------------
--*************************************************************************************************
   GTP_TILE_INST : AURORA_INTERFACE_0_TILE
   generic map
   (
          --_______________________ Simulation-Only Attributes __________________
          TILE_SIM_GTPRESET_SPEEDUP    => SIM_GTPRESET_SPEEDUP
   ) 
port map (
          ------------------------ Loopback and Powerdown Ports ----------------------
          LOOPBACK0_IN                  => LOOPBACK_IN_0,
          LOOPBACK1_IN                  => LOOPBACK_IN_1,
         RXPOWERDOWN0_IN(0)            => POWERDOWN_IN_0,
         RXPOWERDOWN0_IN(1)            => POWERDOWN_IN_0,
			RXPOWERDOWN1_IN(0)            => POWERDOWN_IN_1,
			RXPOWERDOWN1_IN(1)            => POWERDOWN_IN_1,
         TXPOWERDOWN0_IN(0)            => POWERDOWN_IN_0,
         TXPOWERDOWN0_IN(1)            => POWERDOWN_IN_0,
         TXPOWERDOWN1_IN(0)            => POWERDOWN_IN_1,
			TXPOWERDOWN1_IN(1)            => POWERDOWN_IN_1,
          ----------------------- Receive Ports - 8b10b Decoder ----------------------
          RXCHARISCOMMA0_OUT             => RXCHARISCOMMA_OUT_0 ,
          RXCHARISCOMMA1_OUT             => RXCHARISCOMMA_OUT_1,
          RXCHARISK0_OUT                 => RXCHARISK_OUT_0,
          RXCHARISK1_OUT                 => RXCHARISK_OUT_1,
          RXDISPERR0_OUT                 => RXDISPERR_OUT_0,
          RXDISPERR1_OUT                 => RXDISPERR_OUT_1,
          RXNOTINTABLE0_OUT              => RXNOTINTABLE_OUT_0,
          RXNOTINTABLE1_OUT              => RXNOTINTABLE_OUT_1,
         ------------------- Receive Ports - Channel Bonding Ports ------------------
         ------------------- Receive Ports - Clock Correction Ports -----------------
          RXCLKCORCNT0_OUT               => open,
          RXCLKCORCNT1_OUT               => open,
         --------------- Receive Ports - Comma Detection and Alignment --------------
          RXBYTEREALIGN0_OUT             => RXREALIGN_OUT_0 ,
          RXBYTEREALIGN1_OUT             => RXREALIGN_OUT_1 ,
          RXENMCOMMAALIGN0_IN           => ENMCOMMAALIGN_IN_0,
          RXENMCOMMAALIGN1_IN           => ENMCOMMAALIGN_IN_1,
          RXENPCOMMAALIGN0_IN           => ENPCOMMAALIGN_IN_0,
          RXENPCOMMAALIGN1_IN           => ENPCOMMAALIGN_IN_1,
         ------------------- Receive Ports - RX Data Path interface -----------------
          RXDATA0_OUT                    => RXDATA_OUT_0,
          RXDATA1_OUT                    => RXDATA_OUT_1,
          RXRESET0_IN                   => RXRESET_IN_0 ,
          RXRESET1_IN                   => RXRESET_IN_1 ,
          RXUSRCLK0_IN                  => RXUSRCLK_IN_0,
          RXUSRCLK1_IN                  => RXUSRCLK_IN_1 ,
          RXUSRCLK20_IN                 => RXUSRCLK2_IN_0 ,
          RXUSRCLK21_IN                 => RXUSRCLK2_IN_1 ,
         ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
          RXN0_IN                       => RX1N_IN_0,
          RXN1_IN                       => RX1N_IN_1,
          RXP0_IN                       => RX1P_IN_0,
          RXP1_IN                       => RX1P_IN_1,
         -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
          RXBUFSTATUS0_OUT(2)           => RXBUFERR_OUT_0 ,
          RXBUFSTATUS0_OUT(1 downto 0)  => open_rxbufstatus_0(1 downto 0),
          RXBUFSTATUS1_OUT(2)           => RXBUFERR_OUT_1,
			 RXBUFSTATUS1_OUT(1 downto 0)  => open_rxbufstatus_1(1 downto 0),

          TXBUFSTATUS0_OUT(1)           => TXBUFERR_OUT_0 ,
          TXBUFSTATUS0_OUT(0)           => open_txbufstatus_0,
          TXBUFSTATUS1_OUT(1)           => TXBUFERR_OUT_1,
          TXBUFSTATUS1_OUT(0)           => open_txbufstatus_1,
         ----------------- Receive Ports - RX Polarity Control Ports ----------------
          RXPOLARITY0_IN                => RXPOLARITY_IN_0,
          RXPOLARITY1_IN                => RXPOLARITY_IN_1,
         --------------------- Shared Ports - Tile and PLL Ports --------------------
          CLK00_IN                      => REFCLK,
          CLK01_IN                      => REFCLK,

          GTPRESET0_IN                   => GTPRESET_IN,
          GTPRESET1_IN                   => GTPRESET_IN,
          PLLLKDET0_OUT                  => plllkdet_lane0_i,
          PLLLKDET1_OUT                  => plllkdet_lane1_i,
          RESETDONE0_OUT                 => resetdone0_i,
          RESETDONE1_OUT                 => resetdone1_i,
         ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
          TXCHARISK0_IN                 => TXCHARISK_IN_0,
          TXCHARISK1_IN                 => TXCHARISK_IN_1,
         ------------------ Transmit Ports - TX Data Path interface -----------------
          TXDATA0_IN                    => TXDATA_IN_0,
          TXDATA1_IN                    => TXDATA_IN_1,
          GTPCLKOUT0_OUT                => GTPCLKOUT_OUT_0,
          GTPCLKOUT1_OUT                => GTPCLKOUT_OUT_1,
          TXRESET0_IN                   => TXRESET_IN_0 ,
          TXRESET1_IN                   => TXRESET_IN_1 ,
          TXUSRCLK0_IN                  => TXUSRCLK_IN_0,
          TXUSRCLK1_IN                  => TXUSRCLK_IN_1,
          TXUSRCLK20_IN                 => TXUSRCLK2_IN_0,
          TXUSRCLK21_IN                 => TXUSRCLK2_IN_1,
         --------------- Transmit Ports - TX Driver and OOB signalling --------------
          TXN0_OUT                       => TX1N_OUT_0,
          TXN1_OUT                       => TX1N_OUT_1,
          TXP0_OUT                       => TX1P_OUT_0,
          TXP1_OUT                       => TX1P_OUT_1
);

end BEHAVIORAL;   
